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WIRELESS COMMUNICATIONS DIVISION
PCS LNA GND 16 GND VDD PCS 14 MODE CTL 13
15
TQ3M31
DATA SHEET
12 PCS LNA OUT
PCS_LNA input
1
GND
2
11
GND
Dual Band LNA: 2.8V Cellular and PCS Band CDMA/AMPS LNA IC
GND
3
10
GND
Cell_LNA input
4
9
Cell LNA OUT
Features
5 Cell LNA GND 6 GND 7 Vdd Cell 8
Small size: Leadless 3x3mm
Gain CTL
Product Description
Single 2.8V operation Low-current operation Gain Select Mode Select High IP3 performance Few external components
The TQ3M31 is a 2.8V, RF dual band LNA IC designed specifically for Cellular &PCS band CDMA/AMPS applications. It's RF performance meets the requirements of products designed to the IS-95 and AMPS standards. The TQ3M31 is designed to be used with the TQ5131 (Cellular CDMA/AMPS mixer) and the TQ5631 (PCS CDMA mixer) which provides a complete Tri-Mode CDMA receiver for 800MHz dualmode and 1900MHz phones. The LNA incorporates on-chip switches which determine CDMA, AMPS, and bypass mode select. When used with the TQ5131 and TQ5631, four gain states are available in each band. The RF output port is internally matched to 50 , greatly simplifying the design and keeping the number of external components to a minimum. The TQ3M31 achieves good RF performance with low current consumption, supporting long standby times in portable applications. Coupled with the very small MLF 3x3 package, the part is ideally suited for Cellular & PCS band mobile phones. Electrical Specifications1
Parameter Gain Noise Figure Input 3rd Order Intercept 881MHz 1960MHz 881MHz 1960MHz 881MHz 1960MHz DC supply Current 881MHz 1960MHz Min Typ 13.0 13.5 1.4 1.5 12.5 9.0 10.0 11.0 Max Units dB dB dB dB dBm dBm mA mA
Applications
IS-95 CDMA Mobile Phones AMPS Mobile Phones Dual Mode CDMA Cellular applications Dual Band CDMA Cellular & PCS 832-870MHz CDMA applications 1930-1990MHz CDMA applications
Note 1: Test Conditions: Vdd=2.8V, Tc=25C, CDMA High Gain state.
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TQ3M31 Data Sheet
Electrical Characteristics
Parameter Cellular LNA: RF Frequency Conditions Min. 832 1930 Typ/Nom 881 1960 Max. 894 1990 Units MHz MHz
PCS LNA: RF Frequency CDMA Mode-High Gain
Gain Noise Figure Input IP3 LNA IN Return Loss (with external matching) LNA OUT Return Loss Supply Current 881MHz 1960MHz 881MHz 1960MHz 881MHz 1960MHz All modes, both bands All modes, both bands 881MHz 1960MHz
12.0 12.0
13.0 13.5 1.4 1.5 1.8 2.0
dB dB dB dB dBm dBm dB dB
10.0 8.0 10 10
12.5 9.0
10.0 11.0
13.0 13.0
mA mA
Bypass Mode
Gain Noise Figure Input IP3 Supply Current 881MHz 1960MHz 881MHz 1960MHz 881MHz 1960MHz 881MHz 1960MHz 18.0 18.0 1.0 1.0 2.0 2.0 -6.0 -3.5 -5.0 -2.0 5.0 2.0 6.0 3.2 dB dB dB dB dBm dBm mA mA
High Gain Low Linearity Mode
Gain Noise Figure Input IP3 Supply Current Supply Voltage Logic low input Logic high input
Note 1: Test Conditions: Vdd=2.8V, TC = 25 C, unless otherwise specified. Note 2: Min/Max limits are at +25C case temperature, unless otherwise specified.
881MHz 1960MHz 881MHz 1960MHz 881MHz 1960MHz 881MHz 1960MHz 2.7 0 Vcc-0.25
11.0 11.5 1.6 1.7 7.5 6.0 4.5 4.5 2.8 3.3 0.25 Vcc
dB dB dB dB dBm dBm mA mA V V V
2
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TQ3M31 Data Sheet
Absolute Maximum Ratings
Parameter DC Power Supply Power Dissipation Operating Temperature Storage Temperature Signal level on inputs/outputs Voltage to any non supply pin Value 5.0 250 -30 to 85 -60 to 150 +20 +0.3 Units V mW C C dBm V
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TQ3M31 Data Sheet
Typical Performance
Cellular Band Test Conditions, unless Otherwise Specified: Vdd=2.8V, Tc=+25C, RF=881MHz CDMA High Gain Mode Gain v Freq v Temp 15.00 14.50 14.00 13.50 13.00 12.50 12.00 11.50 11.00 10.50 10.00 869 875 881 Frequency (MHz) CDMA High Gain Mode IIP3 v Freq v Temp 14.00 13.50 13.00 IIP3 (dBm) Gain (dB) 12.50 12.00 11.50 11.00 10.50 10.00 869 875 881 887 893 Frequency (MHz) CDMA High Gain Mode Noise Figure v Freq v Temp 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 869 875 881 887 Frequency (MHz)
-30C +25C +85C
CDMA High Gain Mode Idd v Vdd v Temp
12.00 11.50 11.00 Idd (mA)
-30C +25C +85C
Gain (dB)
10.50 10.00 9.50 9.00 8.50 2.7 2.8 3
-30C +25C +85C
887
893
3.15
Voltage (Volts)
High Gain Low Linearity Mode Gain v Freq v Temp
12.50 12.00 11.50 11.00 10.50 10.00 9.50 869 875 881 887 893
Frequency (MHz) High Gain Low Linearity Mode IIP3 v Freq v Temp
-30C +25C +85C
-30C +25C +85C
9.50 9.00 8.50 8.00 7.50 7.00 6.50 6.00 5.50 5.00 869 875 881 887 Frequency (MHz)
Noise Figure (dB)
IIP3 (dBm)
-30C +25C +85C
893
893
4
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TQ3M31 Data Sheet
High Gain Low Linearity Mode Noise Figure v Freq v Temp Bypass Mode IIP3 v Freq v Temp
2.50 Noise Figure (dB) 2.00 1.50 1.00 0.50 0.00 869 875 881 887 893 Frequency (MHz)
High Gain Low Linearity Mode Idd v Vdd v Temp 4.20 4.10 Noise Figure (dB) 4.00 Idd (mA) 3.90 3.80 3.70 3.60 3.50 3.40 2.7 2.8 3 3.15 Voltage (Volts)
-30C +25C +85C -30C +25C +85C
37.00 36.00 35.00
IIP3 (dBm)
34.00 33.00 32.00 31.00 30.00 869 875 881 887 893 Frequency (MHz)
Bypass Mode Noise Figure v Freq v Temp 7.00 6.00 5.00 4.00 3.00 2.00 1.00 0.00 869 875 881 887 893 Frequency (MHz)
-30C +25C +85C -30C +25C +85C
Bypass Mode Gain v Freq v Temp
Bypass Mode Idd v Vdd v Temp 1.60
-30C +25C +85C
-3.80 -4.00 -4.20 Gain (dB) -4.40 -4.60 -4.80 -5.00 -5.20 -5.40 869 875 881 887 893 Frequency (MHz)
1.40 1.20 Idd (mA) 1.00 0.80 0.60 0.40 0.20 0.00 2.7 2.8 3 Voltage (Volts) 3.15
-30C +25C +85C
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5
TQ3M31 Data Sheet
Typical Performance
PCS Band Test Conditions, unless Otherwise Specified: Vdd=2.8V, Tc=+25C, RF=1960MHz
CDMA High Gain Mode Gain v Freq v Temp 15.00 14.50 14.00 13.50 13.00 12.50 12.00 11.50 11.00 10.50 10.00 1930 1945 1960 1975 Frequency (MHz) CDMA High Gain Mode IIP3 v Freq v Temp 10.00 9.50 IIP3 (dBm) 11.50 11.00 Idd (mA) 10.50 10.00 9.50 9.00 8.50 1990 2.7 2.8 3 3.15 Voltage (Volts) High Gain Low Linearity Mode Gain v Freq v Temp
-30C +25C +85C
CDMA High Gain Mode Idd v Vdd v Temp
Gain (dB)
-30C +25C +85C
12.00 11.50 11.00 Gain (dB) 10.50 10.00 9.50 9.00 8.50 8.00
1930 1945 1960 1975 1990
-30C +25C +85C
9.00 8.50 8.00 7.50 7.00 Frequency (MHz) CDMA High Gain Mode Noise Figure v Freq v Temp 2.50
-30C +25C +85C
1930
1945
1960
1975
1990
Frequency (MHz)
High Gain Low Linearity Mode IIP3 v Freq v Temp 8.00 7.50 IIP3 (dBm) 7.00 6.50 6.00 5.50 1990 5.00 1930 1945 1960 1975 1990 Frequency (MHz)
-30C +25C +85C
Noise Figure (dB)
2.00 1.50 1.00 0.50 0.00 1930 1945 1960 1975 Frequency (MHz)
-30C +25C +85C
6
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TQ3M31 Data Sheet
High Gain Low Linearity Mode Noise Figure v Freq v Temp 3.00 2.50 Noise Figure (dB) IIP3 (dBm) 2.00 1.50 1.00 0.50 0.00 1930 1945 1960 1975 Frequency (MHz) High Gain Low Linearity Mode Idd v Vdd v Temp 5.00 4.50 Idd (mA) 4.00 3.50 3.00 2.50 2.7 2.8 3 3.15 Voltage (Volts) Bypass Mode Gain v Freq v Temp 0.00 -0.50 -1.00 Gain (dB) -1.50 -2.00 -2.50 -3.00 -3.50 1930 1945 1960 1975 1990 Frequency (MHz)
-30C +25C +85C -30C +25C +85C -30C +25C +85C
Bypass Mode IIP3 v Freq v Temp 40.00 38.00 36.00 34.00 32.00 30.00 28.00 26.00 24.00 22.00 20.00 1930 1945 1960 1975 Frequency (MHz) Bypass Mode Noise Figure v Freq v Temp
-30C +25C +85C
1990
1990
5.00 4.50 4.00 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 1930 1945 1960 1975 Frequency (MHz)
Bypass Mode Idd v Vdd v Temp 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 2.7 2.8 3 Voltage (Volts)
Noise Figure (dB)
-30C +25C +85C
1990
Idd (mA)
-30C +25C +85C 3.15
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TQ3M31 Data Sheet
Application/Test Circuit
Vdd_PCS R2 Mode_CTL
C8 Lbrd
C5
PCS LNA GND L1 PCS_LNA_in C1 PCS RF in
GND
PCS Vdd
Mode Ctl PCS RF out PCS LNA output
PCS LNA
GND
GND
GND
Cell LNA
GND
L2 Cell_LNA_in C2
Cell RF in Cell LNA GND GND Cell Vdd Gain Ctl
Cell RF out
Cell LNA output
Lbrd C7 R1 Vdd_Cell C4
Gain_CTL
Bill of Material for TQ3M31 LNA Application/Test Circuit
Component Receiver IC Capacitor Capacitor Capacitor Capacitor Capacitor Resistor Inductor Inductor Inductor Reference Designator U1 C1 C2 C3, C4, C5, C6 C7 C8 R1, R2 L1 L2 Lbrd Part Number TQ3M31 1.2pF 2.2pF 1000pF 39pF 10pF 3.3 4.7nH 18nH See application note Value Size Leadless 3x3mm 0402 0402 0402 0402 0402 0402 0603 0603 Manufacturer TriQuint Semiconductor
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TQ3M31 Data Sheet
TQ3M31 Product Description
The TQ3M31 LNA uses two cascode low noise amplifiers along with signal path switching. Two bias control circuits set each LNA's quiescent current for each mode and ensure peak performance over process and temperature, see Figure 1. In the application, a switch control logic linked to the mode control and gain control pins sets the device to the desired mode. See Table 1 for truth table. Each LNA is selected by applying the supply voltage to the Vdd PCS or Cell pin as desired. In the high-gain and high-gain-low-linearity modes, switches S1, S2, S5 (only on high band) and S6 are closed, with switches S3 and S4 opened. In the bypass mode, switches S1, S2, and S5 are opened, with switches S3, S4 and S6 closed. Internal switches ensure there are no parasitic feedback paths for the RF signal. In the AMPS mode, control logic switches the LNA into a low current bias condition. Only four external components are needed for the input and output match of the LNA. The chip uses an external cap and inductor for each LNA input match to pin 1 and 4. The outputs are internally matched to 50 ohms at pin 12 and 9. A Vdd bypass cap is required close to each of the pins 7 and 14. External degeneration of the cascode is required between pin 5&16 and ground. However, a small amount of PC board trace can be used as the inductor. Alternatively, if an extra component can be tolerated, a small value chip inductor could be used. See Figure 2
Vdd_PCS R2 Mode_CTL
C8 Lbrd
C5
16 L1 PCS_LNA_in C1 1
15
S5 S3
14
13
S4
12
S6 S1 S2
PCS LNA output
PCS LNA
2
Bias Control
11
Switch Control Logic
3
Bias Control
10
Cell LNA
S1 S2 S6
L2 Cell_LNA_in C2 5 6 4
S3
9
S4
Cell LNA output
7
8
Lbrd C7 R1 Vdd_Cell C4
Gain_CTL
Figure 1 TQ3M31 Simplified Schematic
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TQ3M31 Data Sheet
Operation
MODE PCS HG PCS HGLL PCS Bypass Cell HG Cell HGLL Cell Bypass Gain_Ctl 0 0 1 0 0 1 Mode Ctl 0 1 1 0 1 1 Cell Vdd 0 0 0 Vdd Vdd Vdd PCS Vdd Vdd Vdd Vdd 0 0 0 Typical gain 13.5 (dB) 11.5 (dB) -2 (dB) 13 (dB) 11 (dB) -5 (dB)
Table 1 LNA States and Control Bits
LNA Input Network Design
Input network design for most LNA's is a straightforward compromise between noise figure and gain. The TQ3M31 is no exception, even though it has 3 different modes. The device was designed so that one only needs to optimize the input match in the high gain mode. As long as the proper grounding and source inductance are used, the other two modes will perform well with the same match. It is probably wise to synthesize the matching network component values for some intermediate range of Gamma values, and then by experimentation, find the one which provides the best compromise between noise figure and gain. The quality of the chip ground will have some effect on the match, which is why some experimentation will likely be needed. The input match will affect the output match to some degree, so S22 should be monitored. The values used on our evaluation board may be taken as a starting point. It has to be noted that another input match network was tested (PCS: 7pF series cap & 2.2nH shunt ind; Cell: 5.6nH series ind & 5.6nH shunt ind) but it proved to degrade the NF and IIP3.
Noise Parameter Analysis
A noise parameter analysis is shown below for the high gain and HGLL modes. A "nominal" device was mounted directly on a standard evaluation board without matching network (through connected). The input reference plane was set at pin 1 & 4 and board loss was included in the calculations. C7 was set to 39pf and C8 to 18pF.
Gamma Opt analysis for TQ3M31 High Gain Mode - PCS band
Freq. (MHz) 1800 1960 2040
opt
angle
F min
R noise
Point#
0.38 0.33 0.33
81.2 86.6 91.4
1.19 1.23 1.28
17.4 17.0 15.9
1 2 3
10
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TQ3M31 Data Sheet
Gamma Opt analysis for TQ3M31 HGLL Mode - PCS band
Freq. (MHz) 1800 1960 2040
opt
angle
F min
R noise
Point#
0.46 0.41 0.40
77.0 83.1 86.7
1.61 1.69 1.75
27.2 26.4 24.1
1 2 3
Gamma Opt analysis for TQ3M31 High Gain Mode - Cell band
Freq. (MHz) 700 880 1000
opt
angle
F min
R noise
Point#
0.51 0.45 0.41
37.4 40.5 41.0
1.11 1.04 1.15
26.6 19.4 19.3
1 2 3
Gamma Opt analysis for TQ3M31 HGLL Mode - Cell band
Freq. (MHz) 700 880 1000
opt
angle
F min
R noise
Point#
0.57 0.50 0.50
36.9 40.2 43.8
1.52 1.40 1.47
43.8 31.4 31.1
1 2 3
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TQ3M31 Data Sheet
Gain Control via Pin 5 & 16 Inductance
The source connection of the LNA cascode is brought out separately through pin 5&16. That allows the designer to make some range of gain adjustment. The total amount of inductance present at the source of the cascode is equal to the bond wire plus package plus external inductance. One should generally use an external inductance such that gain in the high gain PCS mode = 13.5dB. Although it is possible to increase the gain of the TQ3M31, 3 effects are to be expected: the NF and IIP3 will be degraded, and the input match may not work for all modes at the same time anymore. The cell band LNA is especially sensitive to this effect. Figure 2 shows how a rectangular PC board trace can be used as the external inductance. It is suggested that such a circuit be used for the initial design prototype. Then the optimum inductance can be found by simply solder bridging across the inductor. The final PC board design can then include the proper-shorted version of the inductor.
Figure 2 Showing Lbrd and Grounding on Evaluation Board
Selection of the Vdd Bypass Cap for Optimum Performance
The Vdd bypass capacitor has the largest effect on the LNA output match, and is required for proper operation. Because the input match affects the output match to some degree as well, the process of picking the bypass cap value involves some iteration. First, an input match is selected which gives adequate gain and noise figure. Then the bypass capacitor is varied to give the best output match. The demo board achieves at least 12dB of return loss for the PCS band, and at least 11.5dB for the Cell band, which is adequate for connection directly to the input of a SAW filter.
Grounding
An optimal ground for the device is important in order to achieve datasheet specified performance. Symptoms of a poor ground include reduced gain and the inability to achieve <2:1 VSWR at the output when the input is matched. It is recommended to use multiple vias to a mid ground plane layer. The vias at pins 2, 3, 10 and 11 to this layer should be as close to the lead pads as possible. Additionally, the ground return on the Vdd bypass cap should provide minimal inductance back to chip pins 2, 3, 10 and 11.
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TQ3M31 Data Sheet
TQ3M31 S-Parameters
Following are S-Parameter graphs for the HG and HGLL modes in both bands. Data was taken on a single "nominal" device at 2.8v Vdd. The reference planes were set at the end of the package pins.
Cell band - High Gain Mode S-parameters
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TQ3M31 Data Sheet
Cell band - HGLL Mode S-Parameters
14
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TQ3M31 Data Sheet
PCS band - High Gain Mode S-parameters
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15
TQ3M31 Data Sheet
PCS band - HGLL Mode S-Parameters
16
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TQ3M31 Data Sheet
Leadless 3x3 mm Package
NOTES 1 ONLY GROUND SIGNAL TRACES ARE ALLOWED DIRECTLY UNDER THE PACKAGE 2 PRIMARY DIMENSIONS ARE IN MILIMETERS ALTERNATE DIMENSIONS ARE IN INCHES
LEADLESS 3X3-16 PCB FOOTPRINT
1.10 [0.043]
0.13 [0.005]
0.25 [0.010] 0.55 [0.022]
A
1.10 [0.043] 0.50 [0.020] PITCH 4X SIDES
0.53 [0.021]
DETAIL A
1.10 [0.043]
PACKAGE OUTLINE
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TQ3M31 Data Sheet
Additional Information
For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: info_wireless@tqs.com Tel: (503) 615-9000 Fax: (503) 615-8900
For technical questions and additional information on specific applications: Email: info_wireless@tqs.com
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright (c) 1998 TriQuint Semiconductor, Inc. All rights reserved. Revision A, June, 2001
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